A simple step to energy-efficient green HPC

While there are several technologies that can be deployed to maximize energy efficiency in HPC there are simple steps that can be taken to maximize energy efficiency and performance.

Reducing I/O bottlenecks and wait time by utilizing high-performance, low-latency interconnects like QDR Infiniband (40Gb/second) can increase energy efficiency by eliminating wasted CPU cycles waiting for data impeded by slow I/O.

Proper design of compute nodes can make a large impact on energy efficiency. A desired memory configuration for a compute node of 12GB could be achieved by using six 2GB memory modules or by using three 4GB memory modules. While both configurations achieve the same memory capacity the six module configuration can consume as much as double of what the three module configuration does. Multiplied by the number of nodes in a cluster and the 7x24x365 duty cycle of most clusters and the impact of components in a compute node configuration is substantial.

A compute cycle wasted due to code inefficiency is a waste of energy, money and unrealized performance. Using an optimized compiler and math libraries will generate more efficient code and greatly reduce waste of compute resources and energy.

Some compiler vendors offer free use of their compilers for educational and non-profit users. Intel is one compiler vendor with such a program. Contact Aeon Computing for more information.

Products page
Quote